1. Field of the Invention
The present invention relates to a method and apparatus for testing a liquid crystal display, and more particularly, to a method and apparatus for testing a liquid crystal display that reduces the number of channels of a probe unit.
2. Discussion of the Related Art
Liquid crystal displays generally display images by controlling the light transmittance of liquid crystal cells according to video signals. An active matrix liquid crystal display, which includes switching elements formed respectively in liquid crystal cells, is suitable to display moving images. Thin film transistors (TFT) are typically used as the switching elements in the active matrix liquid crystal display.
FIG. 1 shows a schematic diagram of an LCD according to the related art.
As shown in FIG. 1, the related art LCD includes a liquid crystal panel 12, a data driver 20, a gate driver 30, and a timing controller 40. The liquid crystal panel 12 includes liquid crystal cells formed in areas defined by n gate lines GL1 to GLn and m data lines DL1 to DLm. The data driver 20 provides analog video signals to the data lines DL1 to DLm. The gate driver 30 provides scanning signals to the gate lines GL1 to GLn. The timing controller 40 arranges and provides source RGB data signals, received from the outside, to the data driver 20. The timing controller 40 generates a data control signal DCS to control the data driver 20 and generates a gate control signal GCS to control the gate driver 30.
The liquid crystal panel 12 includes a transistor array substrate and a color filter array substrate that are laminated together, spacers that maintain a cell gap between the two array substrates, and a liquid crystal that fills in the cell gap.
The liquid crystal panel 12 includes liquid crystal cells formed respectively in areas defined by the n gate lines GL1 to GLn and the m data lines DL1 to DLm and thin film transistors (TFTs) connected respectively to the liquid crystal cells. In response to scanning signals from the gate lines GL1 to GLn, the TFTs provide data signals received from the data lines DL1 to DLm to the liquid crystal cells. Each of the liquid crystal cells includes a common electrode and a pixel electrode connected to a corresponding TFT that face each other with a liquid crystal therebetween. Thus, each liquid crystal cell can be equivalently expressed by a liquid crystal capacitor Clc. Each liquid crystal cell also includes a storage capacitor that is connected to a previous gate line to maintain a data signal with which the liquid crystal capacitor Clc is charged until the liquid crystal capacitor Clc is charged with a next data signal.
The timing controller 40 formats source RGB data signals received from the outside so as to be suitable to drive the liquid crystal panel 12 and provides such formatted source RGB data signals to the data driver 20. Using a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync, the timing controller 40 generates a data control signal DCS and a gate control signal GCS to control the drive timings of the data driver 20 and the gate driver 30.
The gate driver 30 includes a shift register that sequentially generates scanning signals (i.e., high gate pulses) in response to a gate start pulse GSP and a gate shift clock GSC included in the gate control signal GCS from the timing controller 40. The gate driver 30 sequentially provides the high gate pulses to gate lines GL1 to GLn in the liquid crystal panel 12 to turn on TFTs connected to the gate lines GL1 to GLn.
The data driver 20 converts the formatted data signals Data from the timing controller 40 to analog video signals according to the data control signal DCS received from the timing controller 40. The data driver 20 provides the analog video signals, corresponding to a single horizontal line, to the data lines DL1 to DLm every horizontal period during which a single scanning signal is provided. In response to a polarity control signal POL, the data driver 20 reverses the polarity of the analog video signals Data to be provided to the data line DL1 to DLm on a line by line basis.
After the transistor array substrate and the color filter array substrate are laminated together with a liquid crystal therebetween, the transistor array substrate is generally subjected to a test process before the data driver 20 and the gate driver 30 are electrically connected to the transistor array substrate.
In the test process, an auto-probe test apparatus is used to determine if disconnections and point and line defects are present in the liquid crystal panel 12.
FIG. 2 shows a schematic diagram of an apparatus for testing an LCD according to the related art.
As shown in FIG. 2, the related art apparatus for auto-probe testing an LCD includes a stage 50 on which a liquid crystal panel to be tested is placed, a data probe unit 60 that provides test pattern signals to a plurality of vertically divided blocks of the liquid crystal panel placed on the stage 50, a gate probe unit 70 that provides scanning signals to a plurality of horizontally divided blocks of the liquid crystal panel placed on the stage 50, and a controller 80 that provides test pattern signals to the data probe unit 60 and provides scanning signals to the gate probe unit 70.
The stage 50 supports a liquid crystal panel to be tested and illuminates the rear surface of the liquid crystal panel through a lighting device (not shown).
The data probe unit 60 includes a plurality of data connector blocks 62 corresponding respectively to the vertical blocks of the liquid crystal panel. In the following description, it is assumed that the data probe unit 60 includes 12 data connector blocks 62.
As shown in FIG. 3, each of the data connector blocks 62 includes a plurality of data connector pads 64 having the same shape as a plurality of data pads provided in each of the respective data pad portions of the vertical blocks of a liquid crystal panel to be placed on the stage 50. The data connector pads 64 of each data connector block 62 are commonly connected to a single test pattern signal transmission line 82, through which they receive a test pattern signal from the controller 80.
The data probe unit 60 is moved vertically by a drive unit (not shown) so that the data connector pads 64 of the data connector blocks 62 of the data probe unit 60 are brought into contact with the data pads of the vertical blocks of the liquid crystal panel placed on the stage 50. Thus, through each data connector pad 64 of each data connector block 62 of the data probe unit 60, a test pattern signal from the controller 80 is provided to each data pad of each vertical block of the liquid crystal panel placed on the stage 50.
The gate probe unit 70 includes a plurality of gate connector blocks 72 corresponding respectively to the horizontal blocks of the liquid crystal panel. In the following description, it is assumed that the gate probe unit 70 includes 4 gate connector blocks 72.
As shown in FIG. 3, each of the gate connector blocks 72 includes a plurality of gate connector pads 74 having the same shape as a plurality of gate pads provided in each of the respective gate pad portions of the horizontal blocks of a liquid crystal panel to be placed on the stage 50. The gate connector pads 74 of each gate connector block 72 are commonly connected to a single scanning signal transmission line 84 through which they receive a scanning signal from the controller 80.
The gate probe unit 70 is moved vertically by a drive unit (not shown) so that the gate connector pads 74 of the gate connector blocks 72 of the gate probe unit 70 are brought into contact with the gate pads of the horizontal blocks of the liquid crystal panel placed on the stage 50. Thus, through the gate connector pads 74 of the gate connector blocks 72 of the gate probe unit 70, scanning signals from the controller 80 are sequentially provided to the gate pads of the horizontal blocks of the liquid crystal panel placed on the stage 50.
The controller 80 generates and provides twelve test pattern signals to the twelve data connector blocks 62 of the data probe unit 60 through the twelve test pattern signal transmission lines 82, respectively. The controller 80 sequentially generates and provides four scanning signals to the four gate connector blocks 72 of the gate probe unit 70 through the four scanning signal transmission lines 84, respectively.
FIGS. 4A and 4B schematically illustrate a method for testing an LCD using a conventional auto-probe test apparatus.
The method for testing an LCD using the related art auto-probe test apparatus will now be described with reference to FIGS. 4A and 4B.
First, a liquid crystal panel 12 is placed on the stage 50 as shown in FIG. 4A. The liquid crystal panel 12 includes data pad portions 4 that are divided into 12 blocks having a plurality of data pads connected to data lines DL, and gate pad portions 6 that are divided into 4 blocks having a plurality of data pads connected to gate lines GL.
Then, the data probe unit 60 is moved down toward the stage 50 so that the data connector pads 64 of the data connector blocks 62 are electrically connected to the data pads of the vertical blocks of the liquid crystal panel 12 placed on the stage 50. At the same time, the gate probe unit 70 is moved down toward the stage 50 so that the gate connector pads 74 of the gate connector blocks 72 are electrically connected to the gate pads of the horizontal blocks of the liquid crystal panel 12 placed on the stage 50.
Next, the controller 80 provides scanning signals to the gate connector blocks 72 through the scanning signal transmission lines 84 and provides test pattern signals to the data connector blocks 62 through the test pattern signal transmission lines 82. Specifically, as shown in FIG. 5, the controller 80 provides four scanning signals GB1 to GB4 to the gate connector blocks 72 and provides twelve test pattern signals DB1 to DB12 to the data connector blocks 62.
Accordingly, test pattern images corresponding to the test pattern signals are displayed on the liquid crystal panel 12 as shown in FIG. 6.
Specifically, in a first period of a first frame, a first scanning signal GB1 is provided from the first gate connector block 72 to the gate pad portion 6 of the first horizontal block. In synchronization with the first scanning signal GB1, twelve test pattern signals DB1 to DB12 corresponding to white images W are provided from the twelve data connector blocks 62 to the data pad portions 4 of the twelve vertical blocks. Accordingly, in the first period of the first frame, white test pattern images W corresponding to the twelve test pattern signals DB1 to DB12 are displayed on the first horizontal block that receives the first scanning signal GB1.
In a second period of the first frame, a second scanning signal GB2 is provided from the second gate connector block 72 to the gate pad portion 6 of the second horizontal block. In synchronization with the second scanning signal GB2, first, second, eleventh, and twelfth test pattern signals DB1, DB2, DB11, and DB12 corresponding to white images W are provided from the first, second, eleventh, and twelfth data connector blocks 62 to the data pad portions 4 of the first, second, eleventh, and twelfth vertical blocks, while third to tenth test pattern signals DB3 to DB10 corresponding to black images B are provided from the third to tenth data connector blocks 62 to the data pad portions 4 of the third to tenth vertical blocks. Accordingly, in the second period of the first frame, white test pattern images W corresponding to the first, second, eleventh, and twelfth test pattern signals DB1, DB2, DB11, and DB12 are displayed on first, second, eleventh, and twelfth vertical blocks in the second horizontal block that receives the second scanning signal GB2, and black test pattern images B corresponding to the third to tenth test pattern signals DB3 to DB10 are displayed on the other vertical blocks in the second horizontal block.
In a third period of the first frame, a third scanning signal GB3 is provided from the third gate connector block 72 to the gate pad portion 6 of the third horizontal block. In synchronization with the third scanning signal GB3, first, second, eleventh, and twelfth test pattern signals DB1, DB2, DB11, and DB12 corresponding to white images W are provided from the first, second, eleventh, and twelfth data connector blocks 62 to the data pad portions 4 of the first, second, eleventh, and twelfth vertical blocks, while third to tenth test pattern signals DB3 to DB10 corresponding to black images B are provided from the third to tenth data connector blocks 62 to the data pad portions 4 of the third to tenth vertical blocks. Accordingly, in the third period of the first frame, white test pattern images W corresponding to the first, second, eleventh, and twelfth test pattern signals DB1, DB2, DB11, and DB12 are displayed on first, second, eleventh, and twelfth vertical blocks in the third horizontal block that receives the third scanning signal GB3, and black test pattern images B corresponding to the third to tenth test pattern signals DB3 to DB10 are displayed on the other vertical blocks in the third horizontal block.
Finally, in a fourth period of the first frame, a fourth scanning signal GB4 is provided from the fourth gate connector block 72 to the gate pad portion 6 of the fourth horizontal block. In synchronization with the fourth scanning signal GB4, twelve test pattern signals DB1 to DB12 corresponding to white images W are provided from the twelve data connector blocks 62 to the data pad portions 4 of the twelve vertical blocks. Accordingly, in the fourth period of the first frame, white test pattern images W corresponding to the twelve test pattern signals DB1 to DB12 are displayed on the fourth horizontal block in the liquid crystal panel 12 that receives the fourth scanning signal GB4.
In the method for testing an LCD using the related art auto-probe test apparatus, images corresponding to the twelve test pattern signals DB1 to DB12 are displayed on the liquid crystal panel 12 according to scanning signals from the auto-probe test apparatus to examine if disconnections and point and line defects are present in the liquid crystal panel 12.
The related art LCD auto-probe test apparatus and method needs the same number of data connector pads as that of data pads of the data pad portions of the liquid crystal panel 12. Thus, as the number of data pads increases, the number of data connector pads (i.e., the number of channels) in the probe unit increases, thereby increasing the cost of the auto-probe test apparatus.
In addition, as the pitch between data pads is decreased due to an increase in the resolution of the liquid crystal panel 12, it is difficult to accurately align data connector pads with data pads in the related art LCD auto-probe test apparatus and method.